The invention relates to devices for the storage of multiport data, and particularly to a system of registers than can be addressed by an arithmetic and logic unit of a kernel of a digital signal processor (DSP), and including reading the contents of some of these registers.
Conventionally, a processing kernel may manage 16 registers that are grouped together to form a storage device, for example. The purpose of these registers is to store data that can be used in different operations. The storage device comprises a number of output-ports (or read ports), for example 8. Consequently, up to eight registers can be read in one cycle of a clock signal controlling the speed of the processing kernel. And the same register may be read on the eight output ports.
In general, each output port (or read port) is associated with a path gate formed for example of two complementary MOS transistors controlled on their grids. Each register comprises a number of memory points, for example forty, to store 40-bit data. Since each memory point can be read on the eight read ports simultaneously, it is associated with eight path gates. Each of these path gates controls one line on which the 16 corresponding bits of the 16 registers are connected. Thus, a large capacity amplifier is provided to control 8 output ports behind 8 path gates. Since the capacitance of this large amplifier as seen on its input is high, an inverter is arranged between this amplifier and the memory point to protect it.
However, since 16 registers are connected on each read port, the total capacitance of the read port is very high (capacitance of the read port itself added to the 16 path gate drain capacitances). Furthermore, in the worst case, when the same register is read on the 8 read ports, its inverter sees 8 lines each connected to 16 registers. And in this configuration, the total capacitance as seen by the inverter associated with a register is composed of 8 line capacitances added to 128 drain capacitances of the path gate transistors.
And in this case, the gradient of the signal finally read on the output ports lasts for about 7 nanoseconds for a 0.18 micron technology, which is a problem and is usually outside the required specifications that specify that the duration of the gradient shall not exceed 3 nanoseconds for this technology.
Therefore, such devices require specific signal amplification (buffer), which increases the complexity of the device from the point of view of size and manufacturing cost. Furthermore, power consumption of such a device is high when switching output ports.
An object of the invention is to provide a device that does not include the drawbacks described above.
An object of the invention is to provide a registers system comprising a smaller number of components with a much lower gradient on its output ports than in the prior art, typically 2.5 times lower, so as to generate a large time saving.
Another object of the invention is to provide such a system with a low current consumption.
Another object of the invention is to provide decoding associated with this set of registers, which is much faster than the system usually used in prior art.
Therefore the invention provides a data storage device comprising several registers that can be addressed by address words, and connected to p output ports through connections/connecting means that can be configured in response to address words of p registers selected to read the contents of these registers on the p ports respectively.
According to one general characteristic of the invention, all register address words contain a specific bit with a predetermined rank identical for all address words (for example the high order bit) and remaining bits, the registers are connected in pairs on each output port, and each pair of registers contains two registers with address words that only differ in the value of the said specific bit.
Furthermore, for each pair of registers and for each output port, the connecting means comprise a pair of first switching means that can be controlled in a complementary manner by the specific bit in the address word of one of the two registers, and a second switching means connected to the output port considered and that can be controlled from the remaining bits of the address words of the two registers. The first two switching means are connected firstly between the corresponding two registers, and secondly between the corresponding second switching means.
Thus, according to the invention, the registers are combined in pairs and the only difference in their address words, which may be in the hexadecimal format, is in a single bit, for example the high order bit. This means that the two registers can be read through the same switching means decoded by the remaining bits of the address word. Consequently, the number of switching means attached to a read port will be halved.
Furthermore, the two switching means, in other words the switching means that are directly attached to the read ports, will be controlled much more quickly since they only concern the remaining bits in each address word, the specific bit, for example the high order bit, being used to select one of the two registers in a pair of registers directly.
According to one embodiment of the invention, the registers comprise m memory points so as to store data with m bits. Although the invention is vertically applicable for m=1, m is usually more than 1 and may for example be equal to 32 or 40.
The first switching means associated with a register in a pair then comprises m first elementary path gates, connected to the corresponding m memory points in the register. The first switching means associated with the other register in the pair comprises m other first elementary path gates connected to the corresponding m memory points of this register. A first elementary path gate connected to a memory point of the register is controlled in a complementary manner with respect to the other first elementary path gate connected to the corresponding memory point of the other register. Furthermore, the second switching means comprises m second elementary path gates, connected between the said output port considered and m pairs formed from s elementary path gates and the other first elementary path gates.
According to one embodiment of the invention, the device comprises a first elementary inverter connected between each memory point of a register and the p first elementary path gates associated with this register, and a second elementary inverter connected between each second elementary path gate connected to an output port and the pair formed by the first elementary path gate and the other first elementary path gate associated with the other register in the pair of registers.
For example, each first elementary path gate, and each other first elementary path gate may be formed by pairs of complementary MOS transistors. The grids of two opposite types of transistors (NMOS transistor and PMOS transistor), one belonging to one pair and the other belonging to the other pair, are connected together to enable complementary control of the first elementary path gate and of the other first elementary path gate. The first switching means associated with the two registers in a pair are located close to each other, in order to minimize the size of the device advantageously made in the form of an integrated circuit.